cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 1/7 MTN0410L3 preliminary cystek product specification n -channel logic level enhancement mode mosfet MTN0410L3 bv dss 100v i d 3a r dson(max) 280m features ? low gate charge ? simple drive requirement ? pb-free lead plating package equivalent circuit outline MTN0410L3 sot-223 absolute maximum ratings (t c =25 c, unless otherwise noted) g d s d g gate d drain s source parameter symbol limits unit drain-source voltage v ds 100 v gs 20 v gate-source voltage i d 3 continuous drain current @ t c =25 c continuous drain current @ t c =100c i d 2 pulsed drain current *1, 2 i dm 12 a pd 2.7 w total power dissipation @t c =25 w/ c linear derating factor 0.02 operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature *2. pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 2/7 MTN0410L3 preliminary cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 20 c/w thermal resistance, junction-to-ambient, max r th,j-a 45 (note) c/w note : when mounted on a 1 in 2 pad of 2 oz. copper; 120 c/w when mounted on minimum copper pad. characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 100 - - v v gs =0, i d =1ma v gs(th) 1 - 2.5 v v ds =10v, i d =1ma g fs *1 - 4 - s v ds =10v, i d =2.5a i gss - - 100 na v gs = 20, v ds =0 i dss - - 10 a v ds =80v, v gs =0 - - 280 m v gs =10v, i d =2a r ds(on) *1 - - 320 m v gs =5v, i d =1a dynamic qg *1, 2 - 11.2 - qgs *1, 2 - 4.4 - qgd *1, 2 - 3 - nc v ds =80v, v gs =5v, i d =3.5a t d(on) *1, 2 - 9 - tr *1, 2 - 9.4 - t d(off) *1, 2 - 26.8 - t f *1, 2 - 2.6 - ns v ds =30v, i d =1a, v gs =10v, r g =6 , r l =30 ciss - 975 - coss - 38 - crss - 27 - pf v gs =0v, v ds =25v, f=1mhz source-drain diode i s *1 - - 2 i sm *3 - - 8 a v sd *1 - - 1.5 v i s =3a, v gs =0v, tj=25 c note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTN0410L3 sot-223 (pb-free lead plating package) 2500 pcs / tape & reel
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 3/7 MTN0410L3 preliminary cystek product specification typical characteristics
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 4/7 MTN0410L3 preliminary cystek product specification typical characteristics(cont.)
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 5/7 MTN0410L3 preliminary cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 6/7 MTN0410L3 preliminary cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c792l3 issued date : 2010.07.16 revised date : page no. : 7/7 MTN0410L3 preliminary cystek product specification sot-223 dimension *: typical inches millimeters 321 f b a c d e g h a1 a2 i style: pin 1.gate 2.drain 3.source marking: 3-lead sot-223 plastic surface mounted package cystek package code: l3 device name date code inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1142 0.1220 2.90 3.10 g 0.0551 0.0709 1.40 1.80 b 0.2638 0.2874 6.70 7.30 h 0.0098 0.0138 0.25 0.35 c 0.1299 0.1457 3.30 3.70 i 0.0008 0.0039 0.02 0.10 d 0.0236 0.0315 0.60 0.80 a1 *13 o - *13 o - e *0.0906 - *2.30 - a2 0 o 10 o 0 o 10 o f 0.2480 0.2638 6.30 6.70 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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